Recently, studies have been conducted on a semiconductor device having a three-dimensional structure in which fin-type semiconductor layers (active regions) are stacked on a semiconductor substrate.
For example, if each semiconductor layer on the semiconductor substrate is used as a channel of a memory cell (cell transistor), a vertical gate three-dimensional nonvolatile memory referred to as a vertical gate ladder-bit cost scalable memory (VLB) can be constructed. If each semiconductor layer on the semiconductor substrate is used as a conductive line connected to a memory cell (resistance change element), a cross-point type three-dimensional nonvolatile memory can be constructed.
In order to operate a semiconductor device having a three-dimensional structure typified by the above-mentioned nonvolatile memories, a system is needed to selectively access one of semiconductor layers on a semiconductor substrate. There has been known a technique that provides a layer select transistor as one such system. This layer select transistor has a common gate electrode for the semiconductor layers (channels), and is normally on in one of the semiconductor layers and is on/off controllable in the rest of the semiconductor layers.
However, when one of the semiconductor layers is selected by the layer select transistor, it is necessary to arrange the same number of gate electrodes as the number of the stacked semiconductor layers. This causes problems to a selecting operation. For example, an impurity implanted in each semiconductor layer to allow the layer select transistor to be normally on is improperly diffused due to a heat treatment in a wafer process, and parts that originally need to be on/off controlled are normally on.
This problem is more serious when design rules are reduced and the pitch of the arranged gate electrodes is smaller.